Webinar: PCIe Low Power Analysis
Date and Time
4 June 2025, Wednesday
- 01:00PM IST I 03.30PM SGT
- 08:30AM CET I 02.30PM SGT
- 04.30PM JKT/ KST I 05.30PM SGT
In PCIe interfaces, low-power management using side-band signals is a key requirement for the adoption of SSDs in consumer products. PERST#, CLKREQ#, REFCLK, and PWR signals need to be sequenced properly during device power-on and restart. Consumer products routinely enter power-save or low-power states as needed; during this time, REFCLK is turned off to conserve energy. To transition back to normal operating mode, side-band signals and REFCLK must be sequenced within a specified timeframe.
What Will You Learn?
During this webinar, Prodigy Technovations will provide insight into measuring and analyzing PWR, CLKREQ#, REFCLK, and PERST# signals under various device conditions. The session will showcase how the new PGY-PCIeLP-SBA product captures these signals and performs precise timing measurements. You’ll also understand how its powerful debug features help engineers quickly locate failure causes.
This low-cost, portable solution makes it easier to deploy and debug low-power SSDs operating at 32 Gbps data rates.
Agenda
- Overview of side-band signals in PCIe (PERST#, CLKREQ#, REFCLK, PWR)
- Sequencing and behavior during power-on and low-power states
- Challenges in SSD adoption for consumer products
- Demonstration of PGY-PCIeLP-SBA in capturing and analyzing signals
- Debug techniques using precise timing measurements
- Q&A session
We look forward to your participation!