UFS 4.0 Protocol Analyzer

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UFS 4.0 Protocol Analyzer

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UFS 4.0 Protocol Analyzer (PGY-UFS4.0-PA) is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. PGY-UFS4.0-PA, UFS Protocol Analyzer, a value-based analyzer in its class, offers capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of the UFS layer, UniPro layer, and MPHY layer with the flexibility to correlate decoded data across these protocol layers.


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Product Overview

PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers. It allows for instantaneous decoding of UFS, UniPro, and MPHY layers with the flexibility to correlate decoded data across these protocol layers. PGY-UFS4.0-PA supports PWMG1 to HSG5B data rates and two TX, and two RX lane decode. The active probe has minimum electrical loading on the device under test (DUT) and captures protocol data without affecting the performance of DUT. PGY-UFS4.0- PA Protocol Analyzer supports two-lane data. Comprehensive on the fly decoding of UniPro & UFS data enables validation of communication between UFS host and device.

 

PGY-UFS4.0-PA Protocol Analyzer allows Design and Test Engineers to obtain deep insight into UFS host and device communication. MPHY/UniPRO/UFS packet-based triggering allows specific protocol data capture and analysis. PGY-UFS Protocol analyzer instantaneously provides decoding of UFS, UniPro, and MPHY layers with a correlation to MPHY, UniPro, and UFS layers.

Product Features

  • Supports version MPHY 5.0, UniPro 2.0, and UFS v2.1/3.1/4.0
  • Supports PWM G1 to G7 and HS G1, 2, 3, 4, 5 Rate A and B Series
  •  Supports one/two data lanes (2 TX and 2 RX)
  • Flexibility to capture very large data using continuous streaming of Protocol data to host computer with 16GB Internal acquisition memory field upgradeable up to 64GB.
  • Hardware-based resizable circular buffer with pre/post-trigger.
  • Flexibility to decode selected data from a 16GB buffer.
  • Solder down active probe provides high signal fidelity.
  • Decoding at MPHY, UniPro, and UFS layers.
  • Trigger-based on MPHY, UniPro, and UFS layers packet content.
  • Trigger out a signal at the trigger event allows the triggering of other instruments such as an oscilloscope.
  • Interface to host system using USB 3.0.
  • Flexibility to upgrade the hardware firmware using the GbE interface provides easy field up-gradation of FPGA firmware.
  • Decoded data packets can be exported to a text file for further analysis.
  • Lightweight and can be deployed for on-site/ field tests.

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